The following U.S. patent application Ser. No. 09/430,500, “NOVEL JFET STRUCTURE AND MANUFACTURE METHOD FOR LOW ON RESISTANCE AND LOW VOLTAGE APPLICATIONS”, Ho-Yuan Yu, filed 2 Dec. 1999, is incorporated herein by reference for all purposes. The following copending U.S. patent application Ser. No. 09/708,336, “STARTER DEVICE FOR NORMALLY “OFF” JFETS”, Ho-Yuan Yu, filed 7 Nov. 2000, is incorporated herein by reference for all purposes. The following copending U.S. patent application Ser. No. 09/708,336, “SEMICONDUCTOR PACKAGE FOR POWER JFET HAVING COPPER PLATE FOR SOURCE AND WIRE BOND OR RIBBON CONTACT FOR GATE”, Ho-Yuan Yu, filed 2 Mar. 2001, is incorporated herein by reference for all purposes.
1. Field of the Invention
The present invention is related to semiconductor packaging including the manner in which a semiconductor die ismechanically connected to a supporting structure as well as the methods used for making electrical connections to electrode pads on the die.
2. Related Art
With reference to FIG. 1, a semiconductor package 100 according to the prior art is shown. The semiconductor package 100 includes a bottom plate portion 105 and terminals 120, 121. A semiconductor die 130 is disposed on top of the bottom plate portion 105 and fastened thereto, typically using an epoxy material. The semiconductor die 130 includes a metalized region 135 (typically aluminum) defining a connection area for a top surface of the semiconductor die 130. Portions of the terminals 120, 121, bottom plate portion 105, and semiconductor die 130 are encapsulated in a housing 140, typically formed from a moldable material.
In order to obtain an electrical connection between the metalized region 135 and the terminal(s) 121, one or more wires 122 are ultrasonically bonded at one end 123 to the metalized region 135 and at a distal end 124 to the terminal 121. One surface of the semiconductor die 130 is coupled to the bottom plate 105 by means of a conductive material 106. In the case of a die 130 that is a single Junction Field Effect Transistor (JFET), the surface of the die coupled to the bottom plate 105 by means of the conductive material 106 is typically the drain of the FET. The JFET source is typically coupled to the metalized region 135 and the terminal(s) 121 by one or more wires 122 that are ultrasonically bonded at one end 123 to the metalized region 135 and at a distal end 124 to the terminal 121. Contact to the JFET gate is typically made by electrically coupling via a conductive ribbon.
FIG. 2 shows another semiconductor package 200 of the prior art. In order to electrically connect the metalized region 135 with the terminal 121, one or more wires 131 are stitch bonded at locations 132, thereby providing additional paths for current to flow from the semiconductor die 130 to the terminal 121. This marginally reduces the resistance of the current path from the semiconductor die 130 to the terminal 121.
It is desirable to significantly reduce the resistance and inductance of current paths through a power semiconductor package in order to ensure optimum performance of the semiconductor device. Unfortunately, the semiconductor packages of the prior art do not fully achieve this objective because, among other things, the distance D shown in FIG. 1 between one area of the metalized region 135 and the end 123 of the wires 122 increases the resistance of the current path from the metalized region 135 to the terminal 121. This problem is exacerbated when the thickness of the metalized region 135 is relatively small (typically, the thickness is approximately 4 to 8 microns). The relatively thin metalized region 135 in combination with the distance D and the cross sectional profile of the wire bonds 122 results in a relatively high resistance and inductance for the current path there through.
When the semiconductor package 100 includes, for example, an FET semiconductor die 130, the resistance caused by the distance D and the relatively small diameter of the wires 122, 131 adds to the overall resistance of the FET. Indeed, when die 130 is a FET die, the terminals 120 are typically coupled to the drain of the FET while the terminals 121 are coupled to the source of the FET via one or more wire bonds 122. As ON resistances of FET dies become smaller and smaller, the resistance caused by the distance D and the wire bonds 122, 131 become a larger and larger portion of the overall resistance from one terminal 120 to another terminal 121. Of course, the resistance and inductance from terminal to terminal significantly affect the high frequency performance of a semiconductor device such as a power FET.
Some prior art packages have incorporated a large metal strap to obtain an electrical connection between the metalized region 135 and terminal 121. Unfortunately, this technique has only been possible in large semiconductor packages having relatively simple surface structures, such as bipolar junction transistors, diodes, and thyristors. Further, the metal straps were not practical in small outline packages (such as S08, surface mount dual in line packages). The use of a large metal strap in a gated device, such as an FET, has not heretofore been achieved because such devices have relatively complex surface structures. In particular, gated devices typically include a gate runner (or bus), disposed on the surface of the semiconductor die, which traverses the surface such that gate potential is distributed over the surface of the die. Consequently, disposing a large metal strap over the surface of the die has been problematic because the gate runner restricts access to the die surface and could be shorted to the metal strap. Thus, the use of metal straps in gated semiconductor devices has been prohibitive.
Referring again to FIG. 1, coupling the JFET source to the metalized region 135 and the terminal(s) 121 by one or more wires 122 that are ultrasonically bonded at one end 123 to the metalized region 135 places limitations on the design and layout of the semiconductor die. Ultrasonic bonding of the wire 122 at a distal end 124 to the terminal 121 also places restrictions on the overall package design and layout. Making contact to the JFET gate by ultrasonically bonding a conductive ribbon to a designated region on the semiconductor die is subject to similar problems.
Referring again to FIG. 2, electrically connecting the metalized region 135 with the terminal 121 is realized by stitch bonding one or more wires 131 at locations 132. Again, this technique places limitations on the design and layout of the semiconductor die itself. Further, ultrasonic bonding of the wire 131 the terminal 121 also places restrictions on the overall package design and layout. In this configuration, making contact to the JFET gate by ultrasonically bonding a conductive ribbon to a designated region on the semiconductor die remains subject to similar design and layout problems.